The present invention is directed, in general, to semiconductor devices and, more specifically, to a semiconductor device having reduced susceptibility to plasma damage.
The majority of the present day processes used for silicon fabrication, particularly after forming the transistor, have shifted to plasma processes for various beneficial reasons. For example, plasma processes give better deposition and deposition control in structures having high aspect ratios. Lower thermal budgets can also be achieved by using plasma deposition processes. However along with these benefits, plasma processes also have undesirable aspects associated with their use.
When a wafer is exposed to a plasma, it is exposed to a high energy environment containing high energy ions, electrons and neutral radicals. Due to the presence of these ions and electrons, a current flow can be established in the wafer and thus can be established in the transistor devices located on the wafer. If the current flow becomes significant enough, current can flow through a gate dielectric and stress the gate dielectric. If the gate dielectric becomes damaged as a result of this parasitic current flow, it can produce an undesirable number of inoperative or damaged devices, thereby ultimately increasing yield loss or decreasing performance reliability.
To lessen the affect of this undesired current flow, conventional techniques have included connecting electrodes to the body (substrate) through a reverse-biased diode. Such diodes have mitigated the effect of the current developing process. Moreover, the presence of this diode does not affect normal transistor operation, because in the ON state of the transistor, the diode is reverse-biased and the maximum current between the gate and the body is the diode leakage current. In contrast, the diode leakage current is much higher during illumination, which happens during any plasma process. Hence, the undesired current flow through the gate electrode and dielectric is minimal during fabrication.
However, the conventional use of diodes to mitigate the effect of antenna charging is not desirable in all situations. For example, diodes incorporated into transistor arrays consume significant wafer area/volume, thereby decreasing production yield. Such additional consumption of wafer space can also adversely affect performance as a result of the additional capacitance of the diodes (e.g., clock speed can undesirably decrease).
Accordingly, what is needed in the art is a semiconductor device that does not suffer from the deficiencies found in the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device that includes a semiconductor substrate, semiconductor features located thereover and an insulating photoconductive layer coupling the semiconductor features. The photoconductive layer is configured to provide conductivity between the semiconductor features when exposed to plasma, and at least partially isolate the semiconductor features in the absence of the plasma.
In another embodiment, the present invention provides a method of manufacturing a semiconductor device that includes forming semiconductor features over a semiconductor substrate and coupling the semiconductor features via an insulating photoconductive layer. As with the embodiment discussed above, the photoconductive layer is configured to provide conductivity between the semiconductor features when exposed to plasma.
In yet another embodiment, the present invention provides an integrated circuit that includes a semiconductor substrate, a plurality of transistors having semiconductor features located over the substrate and an insulating photoconductive layer coupling the semiconductor features. Once again, the photoconductive layer is configured to provide conductivity between the semiconductor features when exposed to a plasma environment.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.